There are two basic techniques for performing analog-to-digital conversion. An analog-to-digital converter (ADC) using the first technique, known as the Nyquist rate technique, generates a digital signal directly in response to an analog input signal. The Nyquist rate ADC samples the analog input signal at twice the frequency (known as the Nyquist frequency) of the highest expected frequency component of the input signal. The Nyquist rate ADC uses a series of precisely-matched components to digitize the input signal. The resolution and accuracy of the Nyquist rate ADC depend on the matching of these components. However, highly-precise components are difficult to achieve in conventional integrated circuit processing.
An ADC using the second technique, known as the sigma-delta technique, represents the analog input signal by generating a stream of digital samples whose pulse density is a measure of the voltage at the ADC input. The sigma-delta ADC includes a sigma-delta modulator and a decimator. The modulator includes a quantizer which generates a digital output signal in response to a filtered difference between the analog input signal and a feedback signal. The feedback signal is the digital output signal reconverted to an analog signal in a digital-to-analog converter (DAC). The modulator is oversampled, meaning that the sampling rate is above the Nyquist rate. The decimator resamples the output of the modulator and provides an N-bit data word at the Nyquist rate. The sigma-delta technique achieves high resolution by precise timing instead of by precisely-matched components (resistors and capacitors) which are required by the Nyquist rate ADC.
A simple sigma-delta ADC uses a first-order modulator with a single integrator performing the filter function, a one-bit quantizer, and a one-bit DAC. Since the quantizer can provide the output of the modulator at only one of two levels, its operation is necessarily linear. The first-order sigma-delta modulator has high quantization noise at the sampling frequency. The action of the filter in the modulator shapes the quantization noise to be higher at higher frequencies. Thus, the converter is referred to as a noise-shaping ADC. The decimator also includes a filter having a lowpass characteristic with a cutoff frequency at the Nyquist frequency. Since the sampling frequency is much higher than the Nyquist frequency, the filter can usually attenuate this out-of-band quantization noise sufficiently.
A second-order ADC having two filters in the modulator loop has higher out-of-band quantization noise but lower in-band noise than the first-order ADC. Thus, if the out-of-band noise can be sufficiently filtered, the second-order sigma-delta modulator has better performance. The necessary attenuation can be achieved if the decimation filter is one order greater than the order of the modulator. ADCs higher than second order are possible but typically have stability problems, and ADCs using a second-order modulator are popular.
FIG. 1 illustrates in block diagram form an analog-to-digital converter (ADC) 10 using a conventional decimation filter known in the prior art. ADC 10 includes a sigma-delta (.SIGMA.-.DELTA.) modulator 12 and a decimator 14. .SIGMA.-.DELTA. modulator 12 has an input (not shown) for receiving an analog input signal, and an output for providing a one-bit data stream. According to the .SIGMA.-.DELTA. technique, this one-bit data stream has a pulse density which represents the magnitude of the analog signal and is output at a frequency well above the Nyquist frequency. Decimator 14 includes a first filter 15 having a transfer function labelled "H.sub.1 (z)", a down sampler 16, and a second filter 17 having a transfer function labelled "H.sub.2 (z)". Filter 15 has an input for receiving the data stream provided by .SIGMA.-.DELTA. modulator 12, and converts this data stream into an n-bit output signal using transfer function H.sub.1 (z). Down sampler 16 converts the n-bit input signal received at the modulator frequency and converts it into an n-bit output signal at the output (Nyquist) frequency. Filter 17 has an input for receiving the n-bit output of down sampler 16, and converts it into an n-bit output signal labelled "DECIMATED DATA" using transfer function H.sub.2 (z).
Decimator 14 is a conventional decimator using a cascade of integrators and combs (CIC) architecture. The transfer function of filter 15, H.sub.1 (z), forms the integrator portion and is determined by the order of the modulator but for a second-order modulator is expressed as: EQU H.sub.1 (z)=(1/(1-z.sup.-1)).sup.3 [ 1]
wherein z represents the z-domain (sample) variable. The transfer function of filter 17, H.sub.2 (z), forms the comb portion and is expressed as: EQU H.sub.2 (z)=(1-z.sup.-1).sup.3 [ 2]
Filter 15 is typically implemented by three successive integrators, each containing a delay register and a multi-bit adder having a width equal to the output data width. Since filter 15 precedes down sampler 16, it operates at the same clock rate as .SIGMA.-.DELTA. modulator 12 and therefore consumes a significant amount of power. It would be desirable to reduce the amount of power consumed by decimator 14. Such a decimator is provided by the present invention, whose features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.